As is well known, an electromagnetic receiver is an electronic device that receives electromagnetic waves in a certain range of frequencies and converts the information carried by these waves into some kind of a usable form. For example, a receiver that is typically referred to as a “radio receiver” receives electromagnetic waves in the radio range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz). All receivers use antennas to capture the waves and convert them to alternating current (AC) signals, and electronic filters to separate the signals in the desired band of frequencies from all other signals that may be captured by the antenna. In context of receivers, different bands of frequencies are sometimes referred to as a “channels.”
Selectivity performance of a receiver refers to a measure of the ability of the receiver to separate the desired band of frequencies from unwanted interfering signals received at other frequencies. In other words, selectivity defines how effectively a receiver can respond only to the signal of interest that it is tuned to (i.e., signal in the desired band of frequencies) and reject signals in other frequencies. Adjacent Channel Rejection (ACR) and Image Rejection (IR) are two key specifications that directly impact selectivity of a receiver.
Narrow-band (NB) receivers are receivers that are supposed to only detect signals in one or more relatively narrow bands of frequencies, e.g. 3-25 kHz for a radio receiver, while rejecting signals outside of these bands of interest. ACR and IR requirements for receivers targeting NB applications are very stringent because NB receivers demand high attenuation. Implementing an analog only filter is problematic, and arguably not even feasible, because it requires using prohibitively large area on an Integrated Circuit (IC) chip. At the same time, implementing a digital filter for NB receivers, in particular a digital filter that yields high performance, requires relatively small area to be implemented on a chip, and consumes relatively low power, is an extremely challenging task. Improvements could be made with respect to addressing this issue.
Overview
Embodiments of the present disclosure provide mechanisms that enable implementing an electronic filter that may improve on one or more problems described above, in particular with respect to the use of such a filter in NB receivers where the filter would have sufficiently high performance capable of abiding by the stringent ACR and IR requirements of NB receivers while requiring relatively small area and low power. Accordingly, embodiments of the present disclosure provide a digital filter module for use in a receiver, particularly for use in a narrow-band receiver. Design of the module is based on a recognition that providing to the module samples of a signal received by a receiver and sampled at a sampling frequency equal to four times the intermediate frequency of the receiver, eliminating zeros in the filter, and implementing the filter module as a resource-shared second-order filter structure that includes two sections advantageously enables saving some hardware components, particularly some multipliers and adders, in implementing a versatile digital filter module that can function either as two real filters or one complex filter. In this manner, substantial reduction of area and power consumption of the filter module may be achieved, while maintaining sufficiently high filtering performance. Furthermore, implementing the filter structure as infinite impulse response (IIR) filter allows advantageously saving the number of computations.
Accordingly, one aspect of the present disclose provides a digital filter module for use in a receiver, e.g. a narrow-band receiver. The filter module includes a resource-shared, at least second-order (possibly higher-order), filter structure referred to herein either as a “SOS” (for “Second Order Structure”) or a “bi-quad structure”. The SOS is configured to operate, in a first mode, as an all-pole complex IIR filter, and, in a second mode, as two real all-pole IIR filters. The filter module further includes a mode switch configured to set a mode of operation of the SOS to the first mode or the second mode, e.g. by providing a control signal to the SOS to switch mode of operation of the SOS between the first mode and the second mode. The SOS includes a first section and a second section, where the first section is configured to receive digital samples representing real parts of a signal received by the receiver and the second section is configured to receive digital samples representing imaginary parts of the signal received by the receiver. The digital samples received by the SOS are sampled at a sampling frequency equal to four times the intermediate frequency of the receiver.
In some embodiments, each of the first and second sections may include a scaling multiplier, an adder, one or more first memory elements, a first multiplier, and a selector.
In such embodiments, in the first mode of operation described herein, the digital samples representing the real parts of the signal may be processed, sequentially, by the scaling multiplier of the first section (UMS), the adder of the first section (UA), the one or more first registers of the first section (UD11-UD1k), the first multiplier of the first section (UM1), the selector of the second section (LS) configured to select an output of the first multiplier of the first section (UM1) (as a consequence of the mode of operation being set to the first mode, e.g. as a result of the selector receiving a control signal indicating the first mode of operation), and the adder of the second section (LA). On the other hand, the digital samples representing the imaginary parts of the signal may be processed, sequentially, by the scaling multiplier of the second section (LMS), the adder of the second section (LA), the one or more first registers of the second section (LD11-LD1k), the first multiplier of the second section (LM1), the selector of the first section (US) configured to select an output of the first multiplier of the second section (LM1) (as a consequence of the mode of operation being set to the first mode, e.g. as a result of the selector receiving a control signal indicating the first mode of operation), and the adder of the first section (UA).
In one further embodiment, each of the first and second sections may further include one or more second single-sample delay registers (UD21-UD2k; LD21-LD2k) and a second multiplier (UM2; LM2). In such an embodiment, in the first mode, the adder of the first section (UA) may be configured to add the output of the first multiplier of the second section (LM1) (because this output is selected by the selector of the first section (US)) to an output of processing the digital samples representing the real parts of the signal, sequentially, by the scaling multiplier of the first section (UMS), the one or more second registers of the first section (UD21-UD2k) and the second multiplier of the first section (UM2). On the other hand, the adder of the second section (LA) may be configured to add the output of the first multiplier of the first section (UM1) (because this output is selected by the selector of the second section (LS)) to an output of processing the digital samples representing the imaginary parts of the signal, sequentially, by the scaling multiplier of the second section (LMS), the one or more second registers of the second section (LD21-LD2k) and the second multiplier of the second section (LM2).
In some embodiments, in the second mode of operation described herein, the digital samples representing the real parts of the signal may be processed, sequentially, by the scaling multiplier of the first section (UMS), the adder of the first section (UA), the one or more first registers of the first section (UD11-UD1k), the first multiplier of the first section (UM1), the selector of the first section (US) configured to select an output of the first multiplier of the first section (UM1) (as a consequence of the mode of operation being set to the second mode, e.g. as a result of the selector receiving a control signal indicating the second mode of operation), and the adder of the first section (UA). The digital samples representing the imaginary parts of the signal may be processed, sequentially, by the scaling multiplier of the second section (LMS), the adder of the second section (LA), the one or more first registers of the second section (LD11-LD1k), the first multiplier of the second section (LM1), the selector of the second section (LS) configured to select an output of the first multiplier of the second section (LM1) (as a consequence of the mode of operation being set to the second mode, e.g. as a result of the selector receiving a control signal indicating the second mode of operation), and the adder of the second section (LA).
In one further embodiment, each of the first and second sections may further include one or more second single-sample delay registers (UD21-UD2k; LD21-LD2k) and a second multiplier (UM2; LM2). In such an embodiment, in the second mode, the adder of the first section (UA) may be configured to add the output of the first multiplier of the first section (UM1) (because this output is selected by the selector of the first section (US)) to an output of processing the digital samples representing the real parts of the signal, sequentially, by the scaling multiplier of the first section (UMS), the one or more second registers of the first section (UD21-UD2k) and the second multiplier of the first section (UM2). On the other hand, the adder of the second section (LA) may be configured to add the output of the first multiplier of the second section (LM1) (because this output is selected by the selector of the second section (LS)) to an output of processing the digital samples representing the imaginary parts of the signal, sequentially, by the scaling multiplier of the second section (LMS), the one or more second registers of the second section (LD21-LD2k) and the second multiplier of the second section (LM2).
In some embodiments, each of the first and second sections of the resource-shared second order filter structure may be implemented as a Butterworth filter or a Chebyshev type I filter.
In some embodiments, the digital filter module may be configured to operate as a 2k-order filter, where k is an integer equal to or greater than 1.
In another aspect, a receiver, e.g. an electromagnetic receiver, particularly a radio receiver, including a digital filter module as described herein is disclosed.
In some embodiments, the digital filter module may be configured to filter the signal received by the receiver by rejecting or decreasing signal components outside of a first band of frequencies, the receiver further comprising an analog filter configured to filter the signal received by the receiver by rejecting or decreasing signal components outside of a second band of frequencies, the second band of frequencies being larger than the first band of frequencies. For example, the first band of frequencies could be a band between 3 kHz and 25 kHz.
In some embodiments, the receiver may be configured to be operated in a narrow-bandwidth mode and in a wide-bandwidth mode, the receiver further comprising a controller for using, in the narrow-bandwidth mode, the digital filter module to filter the signal received by the receiver, and for using, in the wide-bandwidth mode, the analog filter to filter the signal received by the receiver.
As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied in various manners—e.g. as a method, a system, a computer program product, or a computer-readable storage medium. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” At least some functions described in this disclosure may be implemented as an algorithm executed by one or more processing units, e.g. one or more microprocessors, of one or more computers. In various embodiments, different steps and portions of the steps of each of the methods described herein may be performed by different processing units. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s), preferably non-transitory, having computer readable program code embodied, e.g., stored, thereon. In various embodiments, such a computer program may, for example, be downloaded (updated) to the existing devices and systems (e.g. to the existing receivers or controllers of such receivers, etc.) or be stored upon manufacturing of these devices and systems.
Other features and advantages of the disclosure are apparent from the following description, and from the claims.